Silicon carbide material has excellent physical and electrical characteristics, and has become one kind of ideal semiconductor material for manufacturing a device of high power, high frequency, high voltage, thermostability and anti-radiation owing to its superior physical and chemical properties of wide band gap, high thermal conductivity, high breakdown field, high saturation velocity. high-power, high frequency, high breakdown voltage, high-temperature and radiation resistant device, and has a broad application prospect in military and civil aspects. Silicon carbide MOSFET devices have advantages of a fast switching speed and small on-resistance etc., and may achieve a higher breakdown voltage by a smaller thickness of a drift layer, which reduces a volume of a power switch module and energy consumption, and has obvious advantages in application fields such as a power switch, a converter etc.
During a process for manufacturing a traditional silicon carbide MOSFET device, it is generally required to heavily dope a P+ region to form a good source ohmic contact and to form a short-circuit connection between a source electrode and a P well. Considering a relationship between implantation dose and implantation energy, an implantation depth is generally shallow. A shallow P+ implantation is prone to generate a parasitic transistor effect of NPN and PiN (a parasitic NPN transistor in a blocking state is easy to occur avalanche breakdown, and a parasitic PiN diode is easy to be depleted at a P side, leading to a breakdown phenomenon; the parasitic NPN transistor in a turned on state is easy to be switched on by mistake), especially for a VDMOSFET device. However, if the P+ region is deeply and heavily doped, the implantation depth is close to or beyond a bottom of the P well. For the same ion implantation element, not only a combination of high energy and high dose is required, which greatly increases an implantation time and an implantation cost, but also an activation annealing quality will be affected, and thus performance of the silicon carbide MOSFET device will be affected. By optimizing the P+ region, the silicon carbide MOSFET device provided by the present disclosure may form a good source ohmic contact to decrease an on-resistance and to short the source electrode and the P well to prevent the parasitic transistor effect of the parasitic NPN and PiN, which may take both of turned-on characteristics and the breakdown characteristics of the device into consideration, and may be applied to a high voltage, high frequency silicon carbide MOSFET device.
A self-aligning process may effectively reduce a channel length, and thus reduce channel resistance and improve a switching rate of the device. In a MOSFET manufacturing process, a self-aligned source region implantation is generally implemented by lateral movement in a polysilicon (Poly-Si) thermal oxidation process, so as to form a self-aligned channel, as shown in FIG. 2a. This method has a strict requirement on the Poly-Si thermal oxidation process, and cannot accurately control a size of the formed channel. The self-aligning manufacturing method used in the present disclosure is to form a self-aligned channel by a method of etching a side wall by insulating layer dielectric, as shown in FIG. 2b, which may accurately control the size of the channel to produce a lateral and vertical power MOSFET.